1. Field of the Invention
The present disclosure generally relates to the field of semiconductor manufacturing, and, more particularly, to forming contact levels having a dielectric material system that comprises at least one highly stressed material.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a great number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a semiconductor layer. Due to the high number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require a plurality of additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
Furthermore, the circuit elements are typically embedded in a dielectric material system, which provides the desired degree of passivation and robustness of the circuit elements prior to forming the complex metallization system. Hence, an appropriate contact regime or contact structure is implemented in the dielectric material system that passivates the circuit elements and that will be also referred to herein as an interlayer dielectric material. Due to the continuous shrinkage of the critical dimensions of the circuit elements and thus due to the reduced lateral pitch of closely spaced circuit elements, the contact structure of the semiconductor device, which may be considered as an interface connecting the circuit elements of the device level with the metallization system, has to be adapted to the reduced feature sizes in the device level and the metallization system. For this reason, very sophisticated patterning strategies may have to be applied in order to provide the contact elements with the required density and with appropriate reduced dimensions, at least at the device level side, in order to appropriately connect to the contact regions, such as drain and source regions, gate electrode structures and the like, without contributing to pronounced leakage current paths and even short circuits and the like. In many conventional approaches, the contact elements or contact plugs are typically formed by using a tungsten-based metal together with an interlayer dielectric stack that is typically comprised of silicon dioxide in combination with an etch stop material, such as a silicon nitride material. Due to the very reduced critical dimensions of the circuit elements, such as the transistors, the respective contact elements have to be formed on the basis of contact openings with an aspect ratio which may be as high as approximately 8:1 or more, wherein a diameter of the contact openings may be 0.1 μm or significantly less for transistor devices of, for instance, the 65 nm technology node. In even further sophisticated approaches, and in very densely packed device regions, the width of the contact openings may be 50 nm and less.
In recent developments, the contact level of sophisticated semiconductor devices may also be used for implementing additional mechanisms for enhancing performance of the transistor elements by inducing a desired type of strain in the active regions of the transistors. It is well known that, for a given crystallographic configuration of the active regions of the transistors, the generation of a specific type of strain, at least in the channel region, may have a significant effect on the resulting charge carrier mobility, i.e., on electrons or holes, thereby providing the possibility of increasing the drive current capability and the switching speed of the transistors for otherwise given transistor parameters. For example, for a standard configuration of a silicon material, i.e., a silicon material having a surface in the form of a (100) equivalent crystal plane with the current flow direction of the channel region oriented along a <110> equivalent crystallographic axis, a compressive strain may result in a significant increase of the mobility of holes, thereby enabling improvement in performance of P-channel transistors. Similarly, the generation of a tensile strain component in the channel region may result in an increase of the electron mobility, thereby providing superior performance of N-channel transistors. Since a strained silicon material in the channel region of field effect transistors may be considered as a “new” type of semiconductor material, without actually requiring new base materials and also allowing the application of many well-established process techniques, great efforts have been made in order to develop strain-inducing mechanisms with a high degree of compatibility with conventional transistor configurations.
One promising approach that is frequently applied in sophisticated semiconductor devices is the incorporation of a highly stressed dielectric material into the interlayer dielectric material system, since at least the lower part of this material system is in close proximity to the gate electrode structures and the active region of the transistors, thereby enabling an efficient transfer of stress forces into the active region in order to create the desired strained state therein. As previously discussed, in a conventional interlayer dielectric material system, typically, an etch stop material, for instance provided in the form of a silicon nitride material, may be applied in combination with the actual interlayer dielectric material, for instance in the form of a silicon dioxide material, thereby enabling the complex patterning sequence for forming contact openings having the desired reduced lateral dimensions, as explained above. Consequently, at least the etch stop material may be positioned in close proximity to the transistors and thus may represent an efficient source of creating a desired type of strain in at least some of the transistors. Therefore, in many approaches, the silicon nitride material of the etch stop layer may be formed so as to have a high internal stress level, which may then be efficiently transferred into the active region and may thus finally result in a desired type of strain in the channel region. For example, plasma enhanced chemical vapor deposition (CVD) techniques have been developed in which process parameters are selected such that compressive stress levels of up to 3 GPa or even higher or tensile stress levels of up to 2 GPa and higher may be obtained. Since the internal stress level of the silicon nitride material, in combination with the amount of material, i.e., the thickness of the etch stop layer, may significantly affect the finally obtained strain in the channel region, generally, the process parameters are targeted so as to produce very high internal stress levels since the layer thickness is typically restricted by the complex surface topography in sophisticated semiconductor devices. For example, in densely packed device areas, gate electrode structures of minimum lateral dimensions may have to be positioned in close proximity to each other, thereby actually requiring deposition techniques with superior gap filling capabilities in order to reliably fill the spaces between the closely spaced gate electrode structures without creating deposition-related irregularities. It turns out, however, that desired high stress levels and superior gap filling capabilities upon depositing the silicon nitride material may not be compatible according to presently available deposition recipes so that corresponding irregularities may be generated, in particular in critical device areas having a very pronounced surface topography, wherein these irregularities may interact with the complex patterning process for forming contact elements, thereby resulting in significant yield losses of sophisticated semiconductor devices, as will be described in more detail with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage. As illustrated, the device 100 comprises a substrate 101, above which is provided a semiconductor layer 102, such as a silicon layer, which may form a bulk configuration or a silicon-on-insulator (SOI) configuration in combination with the substrate 101. That is, a bulk configuration is to be understood as a device architecture in which a crystalline semiconductor material of the substrate 101 may be in direct contact with the semiconductor layer 102, in and above which circuit elements, such as transistors, are to be formed. On the other hand, an SOI architecture is to be understood as a device configuration in which a buried insulating layer (not shown) may be formed below the semiconductor layer 102, thereby vertically bordering the semiconductor layer 102. Furthermore, in the manufacturing stage shown, the semiconductor layer 102 may not represent a continuous semiconductor material but may be divided into a plurality of active regions that are laterally delineated by an isolation region 102I, which may be substantially comprised of silicon dioxide and the like. An active region is to be understood as a semiconductor region in and above which at least one transistor is to be provided. For convenience, in FIG. 1a, a single active region 102A is illustrated, in and above which a plurality of transistors 150 are formed.
The transistors 150 comprise closely spaced gate electrode structures 120A, 120B which may have any appropriate configuration as required by the overall device architecture of the device 100. For example, as illustrated, the gate electrode structures 120A, 120B may comprise a gate dielectric material 122, such as a silicon oxide-based material, possibly in combination with a high-k dielectric material, which is to be understood as a dielectric material having a dielectric constant of 10.0 or higher, and the like. Moreover, an electrode material 121, such as a metal-containing electrode material, a semiconductor material and the like, is typically provided, possibly in combination with a further electrode material 123, for instance provided in the form of a metal silicide material. Moreover, a sidewall spacer structure 124, which may comprise two or more individual spacer elements in combination with etch stop liners (not shown), may be provided on sidewalls of the electrode materials 121 and 123. As discussed above, the gate electrode structures 120A, 120B may have a length that is well beyond 100 nm, such as 50 nm and less in very sophisticated semiconductor devices. The gate length of the structures 120A, 120B is to be understood as the horizontal extension of the electrode material 121.
Moreover, the transistors 150 may comprise drain and source regions 151 having any appropriate dopant concentration and profile as required by the general transistor characteristics. Furthermore, contact areas 152 may be provided in the drain and source regions 151, for instance in the form of a metal silicide and the like. Moreover, a channel region 153 is provided between the drain and source regions 151 and has a length that is substantially determined by the length of the gate electrode structures 120A, 120B and the horizontal dopant profile of the drain and source regions 151. As discussed above, the generation of a certain type of strain in the channel region 153 may significantly increase the conductivity thereof, thereby contributing to a superior performance of the transistors 150. For example, when the transistors 150 represent P-channel transistors, a compressive strain in the channel region 153, for instance along the current flow direction, i.e., along the horizontal direction in FIG. 1a, may provide a superior drive current capability of the transistors 150. To this end, a dielectric material 132, such as a silicon nitride material, is frequently provided so as to have a high internal stress level which may act on the gate electrode structures 120A, 120B and the active region 102A, thereby creating a desired type of strain in the channel region 153.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 in a device area that is laterally offset from the active region 102A of FIG. 1a. In the example shown, it may be assumed that the gate electrode structures 120A, 120B extend laterally beyond the active region 102A so that a portion thereof is formed on or above the isolation region 102I. Thus, the gate electrode structures 120A, 120B may have substantially the same configuration as described with reference to FIG. 1a, except for any differences caused by the different nature of the material of the isolation region 102I and the more pronounced surface topography created therein due to the preceding manufacturing sequence for forming the semiconductor device 100. As illustrated pronounced recesses, as indicated by 102R, are formed in the isolation structure 102I which may be significantly more pronounced compared to any recessing in the active region 102A. Consequently, due to the very pronounced surface topography caused by the recesses 102R, the dielectric layer 132 may frequently comprise deposition-related irregularities, such as a void 132V, which may significantly affect the further processing of the device 100, as will be described later on in more detail.
FIG. 1c schematically illustrates a top view of the semiconductor device 100 according to the manufacturing stage as shown in FIGS. 1a and 1b. As illustrated, the active region 102A may be laterally delineated by the isolation region 102I, which in turn may laterally delineate a further active region 102B, as is also previously explained. The active regions 102A, 102B may correspond to transistors of the same conductivity type or to transistors of different conductivity type, depending on the circuit layout of the device 100. Moreover, in the example shown, it may be assumed that the gate electrode structures 120A, 120B may extend across the active region 102A, across a portion of the isolation region 102I and into or across the active region 102B. As indicated, the cross-section as shown in FIG. 1a may correspond to the section as indicted by Ia, while the cross-section of FIG. 1b may correspond to the section of the isolation region 102I, indicated by Ib. Consequently, in some cases, the void 132V may extend along the isolation region 102I from the active region 102A to the active region 102B.
The semiconductor device as shown in FIGS. 1a-1c may be formed on the basis of the following process strategies. The isolation region 102I is typically provided by applying sophisticated lithography techniques for forming appropriate trenches or recesses in the semi-conductor layer 102 (FIG. 1a) and refilling the recesses with an appropriate dielectric material, such as silicon dioxide. Thereafter, any excess material may be removed, for instance by chemical mechanical polishing (CMP) and etch techniques, and appropriate implantation processes in combination with masking regimes are applied in order to incorporate any desired well dopant species into the active regions 102A, 102B (FIG. 1c). Next, an appropriate material system is provided for the gate electrode structures 120A, 120B, which may be accomplished on the basis of superior oxidation, deposition and patterning strategies, depending on the complexity of the resulting gate layer stack. For example, silicon oxide-based materials may be formed by oxidation and/or deposition while any high-k dielectric materials, possibly in combination with conductive cap materials, may be provided on the basis of sophisticated deposition techniques, such as atomic layer deposition (ALD), CVD, sputter deposition and the like. Similarly, silicon material or any other semiconductor material may be provided by CVD techniques in combination with any additional materials, such as dielectric cap materials (not shown), hard mask materials and the like. Thereafter, a complex patterning sequence is applied in order to pattern the electrode materials 121 and possibly any other additional materials so as to have the desired critical dimensions, which may be 100 nm and significantly less, such as 50 nm and less. Thereafter, a portion of the spacer structure 124 may be formed and drain and source dopant species may be incorporated into the active regions 102A, 102B as required. Thereafter, the spacer structure 124 may be completed and any additional drain and source dopant implants may be introduced, followed by any anneal processes, in order to adjust the final horizontal and vertical dopant profile and to reduce implantation-induced damage. Next, the contact areas or metal silicide regions 152 may be formed, if required, for instance by depositing a refractory metal, such as nickel, platinum and the like, and initiating a chemical reaction to obtain the desired metal silicide. In this stage, the metal silicide 123 may also be provided in the gate electrode structures 120A, 120B.
It should be appreciated that, during the entire complex process sequence, a plurality of sophisticated cleaning processes and etch processes are required, which may result in a more or less pronounced loss of materials in the active regions 102A, 102B and in a more pronounced manner in the isolation region 102I. For example, before and/or after any critical processes, typically, efficient cleaning recipes may have to be applied, wherein frequently chemistries, such as hydrofluoric acid and the like, may be applied in order to remove contaminants and the like. In any such reactive processes, a significant portion of material of the isolation region 102I may also be removed, thereby increasingly contributing to the pronounced recesses 102R (FIG. 1b). For example, also prior to forming the metal silicide regions 152 (FIG. 1a), a pronounced cleaning process may be required in order to prepare exposed surface portions of the active regions 102A, 102B (FIG. 1c) for the subsequent silicidation process. Moreover, in many sophisticated approaches, additional strain-inducing mechanisms are implemented, for instance by providing a strain-inducing semiconductor material (not shown) in a portion of active regions, for instance by providing a silicon/germanium material in the drain and source areas of the transistors, so that the strained silicon/germanium material may also apply a desired compressive strain in the channel region. Also in this case, additional etch and cleaning processes are required, which may result in an even more pronounced surface topography of the isolation region 102I, when laterally delineating the active region of P-channel transistors.
Consequently, upon depositing the dielectric material 132 with a high internal stress level, typically process parameters are selected such that a desired high amount of material may be positioned on the active region 102A (FIG. 1a) and thus also between the closely spaced gate electrode structures 120A, 120B. In this case, the deposition process for forming the layer 132 may result in the void 132V (FIG. 1b) between the gate electrode structures 120A, 120B above the isolation region 102I due to the pronounced recess 102R, since a significantly increased aspect ratio is “seen” by the deposition process locally above the isolation structure 102I.
FIG. 1d schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a further dielectric material 133, for instance in the form of a silicon dioxide material, is provided, thereby forming, in combination with the layer 132, an interlayer dielectric material system 130. Furthermore, a contact element 131 is formed in the system 130 so as to connect to the active regions 102A and/or 102B by connecting to the contact area 152. The material 133 may typically be provided on the basis of well-established deposition techniques, such as high density plasma, CVD, sub-atmospheric CVD and the like, in order to provide the material 133 with the required chemical and mechanical characteristics, while these deposition techniques may also provide high deposition rates and superior gap filling behavior. After the deposition of the material 133, the surface thereof may be planarized, for instance by CMP, in order to provide superior conditions for the subsequent complex patterning strategy for forming the contact element 131. To this end, an appropriate etch mask may be formed on the basis of sophisticated lithography techniques, which may involve the deposition of hard mask materials and the like, followed by a complex etch step for etching through the material 133, while using the material 132 as an etch stop material. Thereafter, a different etch chemistry may be applied so as to etch through the layer 132 to connect to the area 152. Thereafter, appropriate deposition recipes may be applied so as to fill the contact opening with an appropriate contact metal, such as tungsten, followed by the removal of any excess material, for instance by CMP, thereby providing the electrically isolated contact element 131. The deposition of the tungsten material may typically be accomplished on the basis of CVD techniques, possibly in combination with the deposition of appropriate barrier and seed materials, wherein, however, a significant deposition may also occur in the void 132v (FIG. 1c) when the preceding process for forming the contact opening may also result in connecting to the void 132V. For example, by a slight misalignment of the contact openings, the void 132V may extend into the active regions 102A, 102B and a “buried” channel is created which may be filled, at least partially, with the contact material upon filling the contact openings.
FIG. 1e schematically illustrates a top view of the semiconductor device 100 according to a manufacturing stage as shown in FIG. 1d. As illustrated, the contact elements 131 may be provided in the active regions 102A, 102B, wherein also the void 132V may have incorporated therein a conductive material, thereby creating a leakage path, which may even result in a short circuit of the active regions 102A and 102B. Consequently, by applying the manufacturing strategy as described above, a significant probability may exist to form unwanted leakage paths caused by the interlayer dielectric material system 130 (FIG. 1d), which may result in significant yield loss, in particular when highly scaled semiconductor devices are considered. The situation becomes even worse when even more sophisticated approaches are used for implementing strain-inducing mechanisms into the interlayer dielectric material system 130, for instance by applying layers of different types of stresses in order to selectively improve performance of N-channel transistors and P-channel transistors, thereby requiring the deposition of one or more additional stressed material layers and the removal of any unwanted portions thereof, which may contribute to even more pronounced patterning related irregularities. Consequently, a plurality of modifications has been proposed in order to reduce the significant risk of creating contact failures. For example, it has been proposed to provide the material layer 132 (FIGS. 1a, 1b) with superior gap filling capability in order to avoid any deposition related irregularities which, however, may result in a significant drop of the internal stress level according to presently available deposition recipes. Similarly, the reduction of the layer thickness may be associated with a significant reduction of the finally obtained strain level.
In other approaches, a thin dielectric liner material is provided in the contact openings prior to the deposition of the contact metal in an attempt to “seal” the contact openings with respect to any buried channels in the interlayer dielectric material. It appears, however, that a reliable sealing of the contact openings may require a significant thickness of the liner material which, however, may result in a degradation of the overall conductivity of the contact elements, in particular if critical lateral dimensions of 50 nm and less are to be implemented. In still further approaches, it may be attempted to identify the corresponding reactive process steps in which a significant loss of material in the isolation structure 102I is created and to provide alternative process recipes, which, however, may be difficult to achieve since usually any alternative cleaning recipes may suffer from a reduced efficiency, thereby contributing to an increased defect rate in earlier manufacturing stages.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.